al-nafisah/fpga-project-analyzer is a Python command-line tool that presents the connection structure of Vivado, Zynq, and PYNQ projects as offline HTML diagrams. According to the repository description, the diagrams are Vivado-style and support step-by-step exploration into the schematic. No separate latest release version is given in FACTS. The repository is MIT licensed and is also distributed in the form of a skill that AI coding agents can use.
The tool presents clock domain crossings, missing pin constraints, reset polarity, address maps, and the like as items to check while walking through the design connections. A clock domain crossing is a point where signals pass back and forth between different clock regions. The README cites cases where missing pin constraints and asynchronous clock crossing problems are found even in designs that Vivado marks as timing-passing. It therefore focuses on identifying structural check candidates that can be missed based on timing pass/fail status alone.
That said, RTL analysis read without Vivado has its limits, and neither the diagrams nor the check results substitute for validating the original design. The README also describes the findings as candidates to be confirmed in the original design rather than confirmed defects. It is therefore more accurate to treat this tool's output as material for finding points that need further review than for asserting design problems.